Journals

• I. Dubey, M. Kumar, P. Bhattacharya, and R. Bhattacharya, “Exploring Differential Evolution Algorithms in Search of Best Test Vector for Digital Circuit Testing.” In: Journal of Electronic Testing: Theory and Applications (Springer Nature), vol. 42, pp. 177-194, 2026, DOI: 10.1007/s10836-026-06217-6.

• P. Bhattacharya, R. Bhattacharya, and H. Deka, “MATLAB-Open Source Tool-Based Framework for Test Generation for Digital Circuits Using Evolutionary Algorithms.” In: Journal of Electronic Testing: Theory and Applications (Springer Nature), vol. 39, no. 5, 2023, DOI: 10.1007/s10836-023-06088-1.

• Rahul Bhattacharya, Subindu Kumar, and Santosh Biswas, “Fault diagnosis in switched-linear systems by emulation of behavioral models on FPGA: A case study of current-mode buck converter,” International Journal of Numerical Modelling: Electronic Networks, Devices and Fields, Wiley, vol. 31, no. 5, pp. 1-27, 2018.

• Rahul Bhattacharya, Subindu Kumar, and Santosh Biswas, “Resource Optimization for Emulation of Behavioral Models of Mixed Signal Circuits on FPGA: A Case Study of DC-DC Buck Converter,“ International Journal of Circuit Theory and Applications, Wiley, vol. 45, no. 11, pp. 1701-1741, 2017.

• R. Bhattacharya, S. Biswas, S. Mukhopadhyay, “FPGA-based chip emulation system for test development of analog and mixed-signal circuits: A case study of buck converter,“ Measurement, Elsevier, vol. 45, issue. 8, pp. 1997-2020, 2012.
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Conferences

• Sumit Saha, Rahul Bhattacharya, “Comparative Computational Study on Optimal Path Planning for an UAV,” IEEE International Conference on Electrical, Electronics, Communication and Computers (ELEXCOM), December 20-22, 2025, Dhanbad, India.

• Maharishi Sonwani, Rahul Bhattacharya, “FPGA Implementation of a Pipelined RV32IM Processor with Dynamic Branch Prediction,” IEEE International Conference on Electrical, Electronics, Communication, and Computers (ELEXCOM), December 20-22, 2025, Dhanbad, India.

• A. Mahawar, A. Rai, S. Sinha, and R. Bhattacharya, “Single and Multiple Fault Detection in Analog Circuits Using V-Transform Coefficients,” in Proc. 2025 Devices for Integrated Circuit (DevIC), Kalyani, India, pp. 10–15, 2025.

• Puja Kumari, Rahul Bhattacharya, “MATLAB-Simulink-Based Framework for Combinational ATPG Applied to Testing of Digital Blocks in Analog and Mixed-Signal Circuits,” 28th International Symposium on VLSI Design and Test (VDAT), September 01-03, 2024, Vellore, India.

• Abuzar Shakeel, Arpita Dey, Rahul Bhattacharya, Roy Vincent, “Emulation of Nonlinear Dynamics of RF Power Amplifier on FPGA,” 9th IEEE International Conference for Convergence in Technology (I2CT), April 05-07, 2024, Page(s): 01-07

• Priyajit Bhattacharya, Abuzar Shakeel, and Rahul Bhattacharya, “Fault Emulation in Digital Circuits using FPGA-based Software-Hardware Co-Simulation,” 11th IEEE International Conference on Signal Processing and Integrated Networks (SPIN), March 21-22, 2024, Page(s): 355-360.

• Rahul Bhattacharya, S.H.M. Ragamai, and Subindu Kumar, “SFG-Based Fault Simulation of Linear Analog Circuits Using Fault Classification and Sensitivity Analysis,” 21^st International Symposium on VLSI Design and Test (VDAT) 2017, CCIS 711, Springer, pp. 179-190, 2017.

• Anjali Rai, Rahul Bhattacharya, “Parametric Fault Detection for Instrumentation Amplifier Circuit,” 2nd IEEE International Conference on Recent Advances and Innovations in Engineering (ICRAIE-2016), December 23-25, 2016, Jaipur, India.

• R. Bhattacharya, S. Kumar, “A New Approach for Modeling Parametric Faults in Linear Analog VLSI Circuits,” 6^th IEEE International Conference on Computers and Devices for Communication (CODEC), December 16-18, 2015, DOI:10.1109/CODEC.2015.7893197.

• R. Bhattacharya, S. Biswas, S. Mukhopadhyay, “FPGA-based Chip Emulation System for Test Development of Analog and Mixed-Signal Circuits,” 18th Annual ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2010, Page: 284.

• M. Rajneesh, R. Bhattacharya, S. Biswas, S. Mukhopadhyay. “A NEW APPROACH FOR TESTING OF DIGITAL MODULES IN MIXED SIGNAL VLSI CIRCUITS.” IEEE Advanced Computing and Communications, 2007. ADCOM 2007, Page(s): 559-566.

• M. Rajneesh, R. Bhattacharya, S. Biswas, S. Mukhopadhyay, “A NEW APPROACH FOR TESTING OF DIGITAL MODULES IN MIXED SIGNAL VLSI CIRCUITS,” IEEE VLSI Design and Test, 2007, Page(s): 196-204.
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